Processor for Controlling Mixing Process (CMP)
The task involves designing a processor for Controlling Mixing Process (CMP) used in various industries like pharmaceutical, food, and cosmetics. These industries rely heavily on mixing ingredients as part of their production process, which involves controlling and monitoring several factors such as ingredient type, weight, volume, start time, speed, duration, temperature, pressure, and energy.
The CMP processor should be versatile enough to be used in different production lines and should allow programmers to write simple programs to control the mixing process. It should also have special instructions to handle various combinations of the mixing process and other supporting instructions necessary for the operation.
The design can include any special functional units, but any specific unit or component included must be described. Any assumptions made during the design process should also be clearly stated.
The Reports, VHDL Codes and vivado project folder included in a git repo : Git-Kavinda/Processor-for-Controlling-Mixing-Process-CMP-: This repository includes the code, reports, and other resources related to my solution for the EEX7436-Processor Design course's 2023 design project at OUSL. (github.com)
Search about the Mixing process in Industry. Introduction about Mixing process and Common attributes used in most of mixers as well as most of industries are included in the this Report.
During this design:
1. Analyzed the problem, identify the requirement of CMP.
2. Designed working procedure of the CMP.
3. Design an ISA for the CMP.
4. Designed the block diagram for the processor indicating all input and output signals.
5. Create VHDL code for each entities.
6. Verify the model using simulations.
7. Error correcting, debugging.
8. Design control unit and model it using VHDL.
9. Synthesize the design and debug the design by observing simulations.
10. Implementation on FPGA board.
Instruction Word content:
| 4 bit | 12 bit |
|---|---|
| Opcode | Operands |
There are 9 Instructions including reset instruction.
| Opcode | Mnemonic | Operands | Bytes | Operation |
|---|---|---|---|---|
| 0XXX | Reset | - | 2 | Reset the processor to initial state. |
| Configuration Instructions | ||||
| 1000 | Add2p | P,I,IX | 2 | Add Items to a Profile P – Profile Number [4] I – Item [3] Outputs: o 0 – Motor o 1 – Vassals o 2 – General Output o 3 - None Input o 4-Temperature sensor o 5-Pressure sensor o 6-Concentration sensor o 7-General Input IX – Index [5] (0-31) o 0 Dedicated to indicates all enable peripheral. |
| 1001 | Point | P,I,IX | 2 | Point to the desired Item before set the values. P – Profile Number I – Item IX – Index *Operands same as Add2P |
| 1010 | Setval | V | 2 | Set the pointed value as given 12-bit value V [12] (0-4095) |
| Control Instructions | ||||
| 1011 | control | P | 2 | On Profile Process P – Profile Number [4] |
| 1100 | Findmean | P,I | 2 | Finding the Mean of given Profile Item List. P – Profile [4] I – Item [2] o 0-Temperature sensor o 1-Pressure sensor o 2-concntration sensor o 3-General Inputs Store the results in mean register, a 8 Bit register. |
| 1101 | compare | V | 2 | Compare the values with Mean register value, and set the compare flag according to following conditions, V[8] |
| 1110 | JIC | addr | 2 | Jump if compare flag is 1 Addr[12] |
| 1111 | waitt | clk | 2 | Wait given Number of clocks. Clk[12] |

Control Unit Controls the all activities of the processor and it maintain the fetch, decode and execution cycle. It control the all buffers, registers and control the input and output process. Program counter controlling, memory controlling, and control each functions using inbuilt FSM. It maintains the timing and synchronization of each blocks.

Below table illustrates the states changes and the signal controlling in control unit.
| Initial State | Idel State | Fetch One: Send address |
|---|---|---|
| PC_rst <='1'; ins_rst <='1'; timer_rst <='1'; in_rdr_reset <='1'; mtep_rst <='1'; Obuf_rst <='1'; Ibuf_rst <='1'; mean_rst <='1'; disen_read_block <= '0'; |
PC_rst <='0'; ins_rst <='0'; timer_rst <='0'; in_rdr_reset <='0'; mtep_rst <='0'; Obuf_rst <='0'; Ibuf_rst <='0'; mean_rst <='0'; |
ROM_rd <= '1'; ins_ld <= '1'; Mean_load <='0'; mtep_load <='0'; PC_ld <= '0'; PC_en <='0'; |
| Fetch Two: Load Data | Decode | |
| --None | ROM_rd <='0'; ins_ld<='0'; ins_reg <= ins; if(ins_reg(0)='0') then Next_state<=Initial; elsif(ins_reg = "1000") then Next_state <= Add2p; elsif(ins_reg = "1001") then Next_state <= Point; elsif(ins_reg= "1010") then Next_state <= Setval; elsif(ins_reg="1011") then Next_state<= control; elsif(ins_reg = "1100") then Next_state<=Findmean; elsif(ins_reg = "1101") then Next_state <= compare; elsif(ins_reg = "1110") then Next_state <= JIC; elsif(ins_reg = "1111") then Next_state <= waitt; else Next_state <= Initial; |
|
| Add2p | Add2p_two | Add2p_three |
| --address is already in instruction reg Q pin. disen_read_block <='1'; flg_wdata <= '1'; flg_wr <= '1'; next_state <= Add2p_two |
C_en <= '1'; --Increment Program counter next_state<=Add2p_three; |
C_en <= '0'; flg_wdata <= '0'; flg_wr <= '0'; disen_read_block <='0'; next_state <= Fetch_one; |
| Point | Point_two | Setval |
| pd_add_load <= '1'; next_state<=Point_two; PC_en <= '1'; |
spd_add_load <= '0'; Pc_en <= '0'; next_state<=Fetch_one; |
spd_wr <= '1'; next_state<=Setval_two; PC_en <= '1'; |
| Setval_two | Setval_three | Control |
| C_en <='0'; next_state<=Setval_three; --save data |
d_wr <= '0'; next_state <= Fetch_one; |
disen_read_block <= '1'; PC_en <= '1'; next_state<=Control_two; |
| Control_two | Findmean | Findmean_2 |
| PC_en <= '0'; disen_read_block<= '0'; next_state<=Fetch_one; |
itm <= sen_req_itm_in; disen_read_block <= '1'; flag_wr<= '0'; idx <= "00000"; PC_en<='1' Next_state<=Findmean2 |
cal_en <= '0' PC_en<='0' if(idx = "11111") then disen_read_block <= '0'; next_state <= Fetch_one; Mean_load <='1'; else flg_mem_radd <= '1' & itm(5:4) & idx; next_state<=findmean22; |
| Findmean22 | Findmean3 | Findmean4 |
| next_state <= Findmean3; -- wait till flg_mem_out | if(flg_rd = '1') then sen_req_itm <= itm(5:4); sen_req_idx <= idx; next_state <= find_mean4; elsif(flg_rd = '0') then idx <= idx+1; next_state <= Findmean2; |
next_state<= find_mean5; --wait untill sensor men out next_state <= Findmean5 |
| Findmean5 | Findmean6 | Findmean7 |
| Ibuf_load <= '1'; next_state <= Findmean6; |
next_state <= Findmean7; | next_state <= Findmean2; cal_en <= '1' idx <= idx+1; |
| Compare | JIC | Wait |
| mtep_load <='1'; next_state <= Fetch_one; |
if(com_fg = '1') then PC_ld <= '1'; next_state <= Fetch_one; else next_state <= Fetch_one; |
timer_ld <='1'; next_state <= waitt2 |
| Waitt2 | ||
| timer_ld <='0'; if(timer_fg = 1) then state_next <= Fetch_one; |
Used to store and control the address that needs to be fetch next from main memory.

Used to store the Currently decoding instructions’ Operand segments. It store the provide the current operand to the appropriate destination blocks. This data movement control by control unit.

Timer used to count the request clock cycles by wait instruction. It is a down counter and control by control unit.

Flag memory used to store the enable actuators and sensors. It is a bit accessible memory unit which has 16 bit width and 12 bit Depth (8 kB). It also can identified the ‘all sensors’ or ‘all actuator’ instructions and provides the output accordingly.

Speed Memory used to store the speed values of actuators. It is a 12bit Width and 11 bit depth memory (3 kB). (Latency : 1 clock)

IO buffers are used to temporary store the input sensor data and output data until done required operations.

Mean temp Register used to store the user provide mean value temporarily until compare. Mean register used to store the calculated mean value. It actually stores the sum of all read values.

Compare unit used to compare the given and calculated mean values. Input reader unit will provide the count of read input values. Therefore, compare unit first multiply the user provided mean value (Mean temp register) by the count. The it compares with the calculated input values summations (Mean register). Then it provides com_falg as below.

Input reader used to read the sensor values when control unit sends enable signal. It provides the count of read sensor values and the sum of each values.


To simulate the processor functionality and make Timing diagrams, create a Test setup as follows.

Here, RAM initialized with this program:
1000 0001 000 00010 -- ADD2P 1 0 3 ;Add motor 2 to profile 1
1000 0001 000 00011 -- ADD2P 1 0 4 ;Add motor 3 to profile 1
1000 0001 100 00000 -- ADD2P 1 0 0 ;Add all temp sensor to profile 1
1001 0001 000 00010 -- Point 1 0 2 ;Point to motor2 profile1
1010 001111111111 -- Setval 511 ; Set value 511 to located point
1001 0001 000 00011 -- Point 1 0 3 ;Point to motor3 profile 1
1010 001001110001 -- Setval 625 ; Set value 625 to located point
1011 000000000001 -- Control 1 ; Start profile 1
1111 000000000111 -- Waitt 7 ; wait 7 clocks
1100 000100000000 -- Findmean 1,0 ;Find mean val of all temp sensor
1101 000011001000 -- compare 200 ; find the mean >200
1110 000000001001 -- JIC 9 ; if mean > given vale, jump to 8
0000 000000000000 -- Reset ; reset
To demonstrate the Sensor values, use another memory element. It act as a sensor driver and provide sensor read value. To verification purpose, initialized this RAM randomly using below python snippet.


The Reports, VHDL Codes and vivado project folder included in a git repo : Git-Kavinda/Processor-for-Controlling-Mixing-Process-CMP-: This repository includes the code, reports, and other resources related to my solution for the EEX7436-Processor Design course's 2023 design project at OUSL. (github.com)